High Performance Embedded Architectures and Compilers (Record no. 15417)
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| -- | 9783540775607 |
| -- | 978-3-540-77560-7 |
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| -- | 10.1007/978-3-540-77560-7 |
| -- | doi |
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| -- | QA76.9.C62 |
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| -- | UMB |
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| -- | COM036000 |
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| 100 1# - | |
| -- | Stenström, Per. |
| -- | editor. |
| 245 10 - | |
| -- | High Performance Embedded Architectures and Compilers |
| -- | [electronic resource] : |
| -- | Third International Conference, HiPEAC 2008, Göteborg, Sweden, January 27-29, 2008. Proceedings / |
| -- | edited by Per Stenström, Michel Dubois, Manolis Katevenis, Rajiv Gupta, Theo Ungerer. |
| 264 #1 - | |
| -- | Berlin, Heidelberg : |
| -- | Springer Berlin Heidelberg, |
| -- | 2008. |
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| -- | online resource. |
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| -- | text |
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| -- | rdacontent |
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| -- | computer |
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| -- | rdamedia |
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| -- | online resource |
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| -- | text file |
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| -- | Lecture Notes in Computer Science, |
| -- | 0302-9743 ; |
| -- | 4917 |
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| -- | Invited Program -- Supercomputing for the Future, Supercomputing from the Past (Keynote) -- I Multithreaded and Multicore Processors -- MIPS MT: A Multithreaded RISC Architecture for Embedded Real-Time Processing -- rMPI: Message Passing on Multicore Processors with On-Chip Interconnect -- Modeling Multigrain Parallelism on Heterogeneous Multi-core Processors: A Case Study of the Cell BE -- IIa Reconfigurable - ASIP -- BRAM-LUT Tradeoff on a Polymorphic DES Design -- Architecture Enhancements for the ADRES Coarse-Grained Reconfigurable Array -- Implementation of an UWB Impulse-Radio Acquisition and Despreading Algorithm on a Low Power ASIP -- IIb Compiler Optimizations -- Fast Bounds Checking Using Debug Register -- Studying Compiler Optimizations on Superscalar Processors Through Interval Analysis -- An Experimental Environment Validating the Suitability of CLI as an Effective Deployment Format for Embedded Systems -- III Industrial Processors and Application Parallelization -- Compilation Strategies for Reducing Code Size on a VLIW Processor with Variable Length Instructions -- Experiences with Parallelizing a Bio-informatics Program on the Cell BE -- Drug Design Issues on the Cell BE -- IV Power-Aware Techniques -- Coffee: COmpiler Framework for Energy-Aware Exploration -- Integrated CPU Cache Power Management in Multiple Clock Domain Processors -- Variation-Aware Software Techniques for Cache Leakage Reduction Using Value-Dependence of SRAM Leakage Due to Within-Die Process Variation -- V High-Performance Processors -- The Significance of Affectors and Affectees Correlations for Branch Prediction -- Turbo-ROB: A Low Cost Checkpoint/Restore Accelerator -- LPA: A First Approach to the Loop Processor Architecture -- VI Profiles: Collection and Analysis -- Complementing Missing and Inaccurate Profiling Using a Minimum Cost Circulation Algorithm -- Using Dynamic Binary Instrumentation to Generate Multi-platform SimPoints: Methodology and Accuracy -- Phase Complexity Surfaces: Characterizing Time-Varying Program Behavior -- VII Optimizing Memory Performance -- MLP-Aware Dynamic Cache Partitioning -- Compiler Techniques for Reducing Data Cache Miss Rate on a Multithreaded Architecture -- Code Arrangement of Embedded Java Virtual Machine for NAND Flash Memory -- Aggressive Function Inlining: Preventing Loop Blockings in the Instruction Cache. |
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| -- | The ?rst two editions of the HiPEAC conference series in Barcelona (2005) and Ghent (2007) have really demonstrated that the topics covered by HiPEAC attract a lot of interest. In the 2007 conference, about 200 people attended the conference and its satellite events. The third HiPEAC conference was held in G¨ oteborg, the second largest city in Sweden. The o?erings of this conference were rich and diverse. We o?ered attendees a set of four workshops on topics that are all central to the HiPEAC roadmap: multi-cores, compiler optimizations, recon?gurable computing, and interconn- tion networks. Additionally, a tutorial on the Sun?ower Toolsuite was o?ered. The conference program was as rich as in the last years. It featured many important and timely topics such as multi-core processors, recon?gurable s- tems, compiler optimization, power-aware techniques and more. The conference also o?ered a keynote speech by Mateo Valero – the Eckert-Mauchly Award winner in 2007. Several social events provided opportunities for interaction and exchange of ideas in informal settings such as a tour at the Universeum – a science exhibition center and aquarium – where the banquet took place as well. This yearwe received77 submissions of which 14 paperswereCommittee - pers. Papers were submitted from 22 di?erent nations (about 40% from Europe, 25% from Asia, 30% from North America and 5% from South America), which is a token of the global visibility of the conference. |
| 650 #0 - | |
| -- | Computer science. |
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| -- | Data transmission systems. |
| 650 #0 - | |
| -- | Logic design. |
| 650 #0 - | |
| -- | Computer Communication Networks. |
| 650 14 - | |
| -- | Computer Science. |
| 650 24 - | |
| -- | Arithmetic and Logic Structures. |
| 650 24 - | |
| -- | Processor Architectures. |
| 650 24 - | |
| -- | Input/Output and Data Communications. |
| 650 24 - | |
| -- | Logic Design. |
| 650 24 - | |
| -- | Computer Communication Networks. |
| 650 24 - | |
| -- | Programming Languages, Compilers, Interpreters. |
| 700 1# - | |
| -- | Dubois, Michel. |
| -- | editor. |
| 700 1# - | |
| -- | Katevenis, Manolis. |
| -- | editor. |
| 700 1# - | |
| -- | Gupta, Rajiv. |
| -- | editor. |
| 700 1# - | |
| -- | Ungerer, Theo. |
| -- | editor. |
| 710 2# - | |
| -- | SpringerLink (Online service) |
| 773 0# - | |
| -- | Springer eBooks |
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| -- | Printed edition: |
| -- | 9783540775591 |
| 830 #0 - | |
| -- | Lecture Notes in Computer Science, |
| -- | 0302-9743 ; |
| -- | 4917 |
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| -- | http://dx.doi.org/10.1007/978-3-540-77560-7 |
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| -- | ZDB-2-LNC |
| 950 ## - | |
| -- | Computer Science (Springer-11645) |
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| -- | 15417 |
| -- | 15417 |
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