Online Public Access Catalogue

System-level Test and Validation of Hardware/Software Systems (Record no. 21648)

MARC details
020 ## -
-- 9781846281457
-- 978-1-84628-145-7
024 7# -
-- 10.1007/1-84628-145-8
-- doi
050 #4 -
-- TK7888.4
072 #7 -
-- TJFC
-- bicssc
072 #7 -
-- TEC008010
-- bisacsh
082 04 -
-- 621.3815
-- 23
100 1# -
-- Sonza Reorda, Matteo.
-- editor.
245 10 -
-- System-level Test and Validation of Hardware/Software Systems
-- [electronic resource] /
-- edited by Matteo Sonza Reorda, Zebo Peng, Massimo Violante.
264 #1 -
-- London :
-- Springer London,
-- 2005.
300 ## -
-- XII, 179 p.
-- online resource.
336 ## -
-- text
-- txt
-- rdacontent
337 ## -
-- computer
-- c
-- rdamedia
338 ## -
-- online resource
-- cr
-- rdacarrier
347 ## -
-- text file
-- PDF
-- rda
490 1# -
-- Springer Series in Advanced Microelectronics,
-- 1437-0387 ;
-- 17
505 0# -
-- Modeling Permanent Faults -- Test Generation: A Symbolic Approach -- Test Generation: A Heuristic Approach -- Test Generation: A Hierarchical Approach -- Test Program Generation from High-level Microprocessor Descriptions -- Tackling Concurrency and Timing Problems -- An Approach to System-level Design for Test -- System-level Dependability Analysis.
520 ## -
-- New manufacturing technologies have made possible the integration of entire systems on a single chip. This new design paradigm, termed system-on-chip (SOC), together with its associated manufacturing problems, represents a real challenge for designers. As well as giving rise to new design practices, SOC is also reshaping approaches to test and validation activities. These are beginning to migrate from the traditional register-transfer or gate levels of abstraction to the system level. Until now, test and validation have not been supported by system-level design tools so designers have lacked the necessary infrastructure to exploit all the benefits stemming from the adoption of the system level of abstraction such as higher functional performance and greater operating speed. Research efforts are already addressing this issue. System-level Test and Validation of Hardware/Software Systems provides a state-of-the-art overview of the current validation and test techniques by covering all aspects of the subject including: • modeling of bugs and defects; • stimulus generation for validation and test purposes (including timing errors; • design for testability. For researchers working on system-level validation and testing, for tool vendors involved in developing hardware-software co-design tools and for graduate students working in embedded systems and SOC design and implementation, System-level Test and Validation of Hardware/Software Systems will be an invaluable source of reference.
650 #0 -
-- Engineering.
650 #0 -
-- Computer hardware.
650 #0 -
-- Computer science.
650 #0 -
-- Condensed matter.
650 #0 -
-- Engineering design.
650 #0 -
-- Electronics.
650 #0 -
-- Systems engineering.
650 14 -
-- Engineering.
650 24 -
-- Circuits and Systems.
650 24 -
-- Electronics and Microelectronics, Instrumentation.
650 24 -
-- Engineering Design.
650 24 -
-- Computer Hardware.
650 24 -
-- Programming Techniques.
650 24 -
-- Condensed Matter.
700 1# -
-- Peng, Zebo.
-- editor.
700 1# -
-- Violante, Massimo.
-- editor.
710 2# -
-- SpringerLink (Online service)
773 0# -
-- Springer eBooks
776 08 -
-- Printed edition:
-- 9781852338992
830 #0 -
-- Springer Series in Advanced Microelectronics,
-- 1437-0387 ;
-- 17
856 40 -
-- http://dx.doi.org/10.1007/1-84628-145-8
912 ## -
-- ZDB-2-ENG
950 ## -
-- Engineering (Springer-11647)
999 ## -
-- 21648
-- 21648

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