Chip Design for Submicron VLSI:CMOS Layout & Simulation
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TextPublication details: Delhi Cengage Learning 2006Description: xiii, 411ISBN: - 9788131501955
| Item type | Current library | Collection | Call number | Status | Date due | Barcode | |
|---|---|---|---|---|---|---|---|
| Books | NMIT | ECE | 621.381 5 UYE (Browse shelf(Opens below)) | Checked out | 2018-02-21 00:00 | 32228 | |
| Books | NMIT | ECE | 621.381 5 UYE (Browse shelf(Opens below)) | Checked out | 2018-02-21 00:00 | 32229 | |
| Books | NMIT | ECE | 621.381 5 UYE (Browse shelf(Opens below)) | Checked out | 2018-09-19 00:00 | 32230 | |
| Reference | NMIT | ECE | 621.381 5 UYE (Browse shelf(Opens below)) | Available | 17430 |
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| 621.381 5 TER Op-Amps: Design Application & Troubleshooting | 621.381 5 TOK Digital Electronics: Principles and Applications | 621.381 5 UYE Chip Design for Submicron VLSI:CMOS Layout & Simulation | 621.381 5 UYE Chip Design for Submicron VLSI:CMOS Layout & Simulation | 621.381 5 UYE Chip Design for Submicron VLSI:CMOS Layout & Simulation | 621.381 5 UYE Chip Design for Submicron VLSI:CMOS Layout & Simulation | 621.381 5 VEN Linear Integrated Circuits and Applications |
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