Transactions on High-Performance Embedded Architectures and Compilers I [electronic resource] /
edited by Per Stenström.
- XV, 361 p. Also available online. online resource.
- Lecture Notes in Computer Science, 4050 0302-9743 ; .
- Lecture Notes in Computer Science, 4050 .
High Performance Processor Chips -- High Performance Processor Chips -- High-Performance Embedded Architecture and Compilation Roadmap -- 1: First International Conference on High-Performance Embedded Architectures and Compilers, HiPEAC 2005. Best Papers -- to Part 1 -- Quick and Practical Run-Time Evaluation of Multiple Program Optimizations -- Specializing Cache Structures for High Performance and Energy Conservation in Embedded Systems -- GCH: Hints for Triggering Garbage Collections -- Memory-Centric Security Architecture -- Power Aware External Bus Arbitration for System-on-a-Chip Embedded Systems -- 2: Optimizing Compilers -- to Part 2 -- Convergent Compilation Applied to Loop Unrolling -- Finding and Applying Loop Transformations for Generating Optimized FPGA Implementations -- Dynamic and On-Line Design Space Exploration for Reconfigurable Architectures -- Automatic Discovery of Coarse-Grained Parallelism in Media Applications -- An Approach for Enhancing Inter-processor Data Locality on Chip Multiprocessors -- 3: ACM International Conference on Computing Frontiers 2006. Best Papers -- to Part 3 -- Hardware/Software Architecture for Real-Time ECG Monitoring and Analysis Leveraging MPSoC Technology -- Using Application Bisection Bandwidth to Guide Tile Size Selection for the Synchroscalar Tile-Based Architecture -- Static Cache Partitioning Robustness Analysis for Embedded On-Chip Multi-processors -- Selective Code Compression Scheme for Embedded Systems -- A Prefetching Algorithm for Multi-speed Disks -- Reconfiguration Strategies for Environmentally Powered Devices: Theoretical Analysis and Experimental Validation.
lastfewdecades. Healsoprovideshisoutlookontheforcesthatwillbeimportant overthenextdecade. Hisarticleappearsasthe?rstregularpaperinthisvolume. AnimportantdeliverablefortheHiPEACNetworkofExcellenceisaroadmap ofthechallengesfacinghigh-performanceembeddedarchitecturesandcompilers. The HiPEAC community has put together a roadmap along ten themes that highlights the research challenges we are faced with in the next decade. I am pleased that the roadmapappears in this volume. It is the second regular paper. Apart from publishing regular papers, Transactions on HiPEAC will so- times publish papers on special topics or highlights from conferences. This v- ume contains three such specialized themes organized into three parts: Part 1, Part 2, and Part 3. Part 1 is devoted to the best papers of the 2005 Inter- tional Conference on High-PerformanceEmbedded Architectures and Compilers (HiPEAC 2005). Part 2 is devoted to the topic of optimizing compilers and is edited by Mike O’Boyle, University of Edinburgh, Fran¸ cois Bodin, IRISA, and Marcelo Cintra, University of Edinburgh. Finally, Part 3 is devoted to the best papers on embedded architectures and compilers from the 2006 ACM Inter- tional Conference on Computing Frontiers and is edited by Sally A. McKee, Cornell University. Organizing speci?c themes in this journal will be a rec- ring activity in the future and I encourage prospective guest editors to propose themes for future volumes. Finally, I have been fortunate to engage a set of distinguished members of our community to form the ?rst editorial board. It is my pleasure to introduce this set of ?ne people.
9783540715283
10.1007/978-3-540-71528-3 doi
Computer science. Data transmission systems. Logic design. Computer Communication Networks. Computer Science. Arithmetic and Logic Structures. Processor Architectures. Input/Output and Data Communications. Logic Design. Computer Communication Networks. Programming Languages, Compilers, Interpreters.