TY  - BOOK
AU  - Sonza Reorda,Matteo
AU  - Peng,Zebo
AU  - Violante,Massimo
ED  - SpringerLink (Online service)
TI  - System-level Test and Validation of Hardware/Software Systems
T2  - Springer Series in Advanced Microelectronics,
SN  - 9781846281457
AV  - TK7888.4 
U1  - 621.3815 23
PY  - 2005///
CY  - London
PB  - Springer London
KW  - Engineering
KW  - Computer hardware
KW  - Computer science
KW  - Condensed matter
KW  - Engineering design
KW  - Electronics
KW  - Systems engineering
KW  - Circuits and Systems
KW  - Electronics and Microelectronics, Instrumentation
KW  - Engineering Design
KW  - Computer Hardware
KW  - Programming Techniques
KW  - Condensed Matter
N1  - Modeling Permanent Faults -- Test Generation: A Symbolic Approach -- Test Generation: A Heuristic Approach -- Test Generation: A Hierarchical Approach -- Test Program Generation from High-level Microprocessor Descriptions -- Tackling Concurrency and Timing Problems -- An Approach to System-level Design for Test -- System-level Dependability Analysis
N2  - New manufacturing technologies have made possible the integration of entire systems on a single chip. This new design paradigm, termed system-on-chip (SOC), together with its associated manufacturing problems, represents a real challenge for designers. As well as giving rise to new design practices, SOC is also reshaping approaches to test and validation activities. These are beginning to migrate from the traditional register-transfer or gate levels of abstraction to the system level. Until now, test and validation have not been supported by system-level design tools so designers have lacked the necessary infrastructure to exploit all the benefits stemming from the adoption of the system level of abstraction such as higher functional performance and greater operating speed. Research efforts are already addressing this issue. System-level Test and Validation of Hardware/Software Systems provides a state-of-the-art overview of the current validation and test techniques by covering all aspects of the subject including: • modeling of bugs and defects; • stimulus generation for validation and test purposes (including timing errors; • design for testability. For researchers working on system-level validation and testing, for tool vendors involved in developing hardware-software co-design tools and for graduate students working in embedded systems and SOC design and implementation, System-level Test and Validation of Hardware/Software Systems will be an invaluable source of reference
UR  - http://dx.doi.org/10.1007/1-84628-145-8
ER  -