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001 978-3-540-32080-7
003 DE-He213
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008 100929s2005 gw | s |||| 0|eng d
020 _a9783540320807
_9978-3-540-32080-7
024 7 _a10.1007/11556930
_2doi
050 4 _aQA76.9.L63
072 7 _aUYF
_2bicssc
072 7 _aCOM036000
_2bisacsh
082 0 4 _a621.395
_223
100 1 _aPaliouras, Vassilis.
_eeditor.
245 1 0 _aIntegrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
_h[electronic resource] :
_b15th International Workshop, PATMOS 2005, Leuven, Belgium, September 21-23, 2005. Proceedings /
_cedited by Vassilis Paliouras, Johan Vounckx, Diederik Verkest.
264 1 _aBerlin, Heidelberg :
_bSpringer Berlin Heidelberg,
_c2005.
300 _aXV, 753 p. Also available online.
_bonline resource.
336 _atext
_btxt
_2rdacontent
337 _acomputer
_bc
_2rdamedia
338 _aonline resource
_bcr
_2rdacarrier
347 _atext file
_bPDF
_2rda
490 1 _aLecture Notes in Computer Science,
_x0302-9743 ;
_v3728
505 0 _aSession 1: Low-Power Processors -- Session 2: Code Optimization for Low-Power -- Session 3: High-Level Design -- Session 4: Telecommunications and Signal Processing -- Session 5: Low-Power Circuits -- Session 6: System-on-Chip Design -- Session 7: Busses and Interconnections -- Session 8: Modeling -- Session 9: Design Automation -- Session 10: Low-Power Techniques -- Session 11: Memory and Register Files -- Poster Session 1: Applications -- Poster Session 2: Digital Circuits -- Poster Session 3: Analog and Physical Design -- Special Session: Digital Hearing Aids: Challenges and Solutions for Ultra Low Power -- Invited Talks.
520 _aWelcome to the proceedings of PATMOS 2005, the 15th in a series of international workshops.PATMOS2005wasorganizedbyIMECwithtechnicalco-sponsorshipfrom the IEEE Circuits and Systems Society. Over the years, PATMOS has evolved into an important European event, where - searchers from both industry and academia discuss and investigate the emerging ch- lenges in future and contemporary applications, design methodologies, and tools - quired for the developmentof upcominggenerationsof integrated circuits and systems. The technical program of PATMOS 2005 contained state-of-the-art technical contri- tions, three invited talks, a special session on hearing-aid design, and an embedded - torial. The technical program focused on timing, performance and power consumption, as well as architectural aspects with particular emphasis on modeling, design, char- terization, analysis and optimization in the nanometer era. The Technical Program Committee, with the assistance of additional expert revi- ers, selected the 74 papers to be presented at PATMOS. The papers were divided into 11 technical sessions and 3 poster sessions. As is always the case with the PATMOS workshops, the review process was anonymous, full papers were required, and several reviews were carried out per paper. Beyond the presentations of the papers, the PATMOS technical program was - riched by a series of speeches offered by world class experts, on important emerging research issues of industrial relevance. Prof. Jan Rabaey, Berkeley, USA, gave a talk on “Traveling the Wild Frontier of Ulta Low-Power Design”, Dr. Sung Bae Park, S- sung, gave a presentation on “DVL (Deep Low Voltage): Circuits and Devices”, Prof.
650 0 _aComputer science.
650 0 _aLogic design.
650 0 _aOperating systems (Computers).
650 0 _aComputer aided design.
650 0 _aComputer engineering.
650 1 4 _aComputer Science.
650 2 4 _aLogic Design.
650 2 4 _aPerformance and Reliability.
650 2 4 _aProcessor Architectures.
650 2 4 _aArithmetic and Logic Structures.
650 2 4 _aComputer-Aided Engineering (CAD, CAE) and Design.
650 2 4 _aElectrical Engineering.
700 1 _aVounckx, Johan.
_eeditor.
700 1 _aVerkest, Diederik.
_eeditor.
710 2 _aSpringerLink (Online service)
773 0 _tSpringer eBooks
776 0 8 _iPrinted edition:
_z9783540290131
830 0 _aLecture Notes in Computer Science,
_x0302-9743 ;
_v3728
856 4 0 _uhttp://dx.doi.org/10.1007/11556930
912 _aZDB-2-SCS
912 _aZDB-2-LNC
950 _aComputer Science (Springer-11645)
999 _c13994
_d13994