000 03804nam a22005655i 4500
001 978-3-540-39097-8
003 DE-He213
005 20201213201035.0
007 cr nn 008mamaa
008 100301s2006 gw | s |||| 0|eng d
020 _a9783540390978
_9978-3-540-39097-8
024 7 _a10.1007/11847083
_2doi
050 4 _aQA76.9.L63
072 7 _aUYF
_2bicssc
072 7 _aCOM036000
_2bisacsh
082 0 4 _a621.395
_223
100 1 _aVounckx, Johan.
_eeditor.
245 1 0 _aIntegrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
_h[electronic resource] :
_b16th International Workshop, PATMOS 2006, Montpellier, France, September 13-15, 2006. Proceedings /
_cedited by Johan Vounckx, Nadine Azemard, Philippe Maurine.
264 1 _aBerlin, Heidelberg :
_bSpringer Berlin Heidelberg,
_c2006.
300 _aXVI, 677 p. Also available online.
_bonline resource.
336 _atext
_btxt
_2rdacontent
337 _acomputer
_bc
_2rdamedia
338 _aonline resource
_bcr
_2rdacarrier
347 _atext file
_bPDF
_2rda
490 1 _aLecture Notes in Computer Science,
_x0302-9743 ;
_v4148
505 0 _aSession 1 – High-Level Design -- Session 2 – Power Estimation / Modeling -- Session 3 – Memory and Register Files -- Session 4 – Low-Power Digital Circuits -- Session 5 – Busses and Interconnects -- Session 6 – Low Power Techniques -- Session 7 – Applications and SoC Design -- Session 8 – Modeling -- Session 9 – Digital Circuits -- Session 10 – Reconfigurable and Programmable Devices -- Poster 1 -- Poster 2 -- Poster 3 -- Keynotes -- Industrial Session.
520 _aWelcome to the proceedings of PATMOS 2006, the 16th in a series of international workshops. PATMOS 2006 was organized by LIRMM with CAS technical - sponsorship and CEDA sponsorship. Over the years, the PATMOS workshop has evolved into an important European event, where researchers from both industry and academia discuss and investigate the emerging challenges in future and contemporary applications, design methodologies, and tools required for the development of upcoming generations of integrated circuits and systems. The technical program of PATMOS 2006 contained state-of-the-art technical contributions, three invited talks, a special session on hearing-aid design, and an embedded tutorial. The technical program focused on timing, performance and power consumption, as well as architectural aspects with particular emphasis on modeling, design, characterization, analysis and optimization in the nanometer era. The Technical Program Committee, with the assistance of additional expert reviewers, selected the 64 papers presented at PATMOS. The papers were organized into 11 technical sessions and 3 poster sessions. As is always the case with the PATMOS workshops, full papers were required, and several reviews were received per manuscript.
650 0 _aComputer science.
650 0 _aMemory management (Computer science).
650 0 _aLogic design.
650 0 _aComputer system performance.
650 0 _aSystems engineering.
650 1 4 _aComputer Science.
650 2 4 _aLogic Design.
650 2 4 _aProcessor Architectures.
650 2 4 _aSystem Performance and Evaluation.
650 2 4 _aArithmetic and Logic Structures.
650 2 4 _aMemory Structures.
650 2 4 _aCircuits and Systems.
700 1 _aAzemard, Nadine.
_eeditor.
700 1 _aMaurine, Philippe.
_eeditor.
710 2 _aSpringerLink (Online service)
773 0 _tSpringer eBooks
776 0 8 _iPrinted edition:
_z9783540390947
830 0 _aLecture Notes in Computer Science,
_x0302-9743 ;
_v4148
856 4 0 _uhttp://dx.doi.org/10.1007/11847083
912 _aZDB-2-SCS
912 _aZDB-2-LNC
950 _aComputer Science (Springer-11645)
999 _c14453
_d14453