| 000 | 05276nam a22005895i 4500 | ||
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| 001 | 978-3-540-69338-3 | ||
| 003 | DE-He213 | ||
| 005 | 20201213201138.0 | ||
| 007 | cr nn 008mamaa | ||
| 008 | 100301s2007 gw | s |||| 0|eng d | ||
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_a9783540693383 _9978-3-540-69338-3 |
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_a10.1007/978-3-540-69338-3 _2doi |
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| 050 | 4 | _aQA76.9.C62 | |
| 072 | 7 |
_aUMB _2bicssc |
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_aUYF _2bicssc |
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_aCOM036000 _2bisacsh |
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| 082 | 0 | 4 |
_a004 _223 |
| 100 | 1 |
_aBosschere, Koen. _eeditor. |
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| 245 | 1 | 0 |
_aHigh Performance Embedded Architectures and Compilers _h[electronic resource] : _bSecond International Conference, HiPEAC 2007, Ghent, Belgium, January 28-30, 2007. Proceedings / _cedited by Koen Bosschere, David Kaeli, Per Stenström, David Whalley, Theo Ungerer. |
| 264 | 1 |
_aBerlin, Heidelberg : _bSpringer Berlin Heidelberg, _c2007. |
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| 300 |
_aXI, 307 p. Also available online. _bonline resource. |
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_atext _btxt _2rdacontent |
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_acomputer _bc _2rdamedia |
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_aonline resource _bcr _2rdacarrier |
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_atext file _bPDF _2rda |
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_aLecture Notes in Computer Science, _x0302-9743 ; _v4367 |
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| 505 | 0 | _aInvited Program -- Keynote: Insight, Not (Random) Numbers: An Embedded Perspective -- I Secure and Low-Power Embedded Memory Systems -- Compiler-Assisted Memory Encryption for Embedded Processors -- Leveraging High Performance Data Cache Techniques to Save Power in Embedded Systems -- Applying Decay to Reduce Dynamic Power in Set-Associative Caches -- II Architecture/Compiler Optimizations for Efficient Embedded Processing -- Virtual Registers: Reducing Register Pressure Without Enlarging the Register File -- Bounds Checking with Taint-Based Analysis -- Reducing Exit Stub Memory Consumption in Code Caches -- III Adaptive Microarchitectures -- Reducing Branch Misprediction Penalties Via Adaptive Pipeline Scaling -- Fetch Gating Control Through Speculative Instruction Window Weighting -- Dynamic Capacity-Speed Tradeoffs in SMT Processor Caches -- Branch History Matching: Branch Predictor Warmup for Sampled Simulation -- Sunflower : Full-System, Embedded Microarchitecture Evaluation -- Efficient Program Power Behavior Characterization -- Generation of Efficient Embedded Applications -- Performance/Energy Optimization of DSP Transforms on the XScale Processor -- Arx: A Toolset for the Efficient Simulation and Direct Synthesis of High-Performance Signal Processing Algorithms -- A Throughput-Driven Task Creation and Mapping for Network Processors -- Optimizations and Architectural Tradeoffs for Embedded Systems -- MiDataSets: Creating the Conditions for a More Realistic Evaluation of Iterative Optimization -- Evaluation of Offset Assignment Heuristics -- Customizing the Datapath and ISA of Soft VLIW Processors -- Instruction Set Extension Generation with Considering Physical Constraints. | |
| 520 | _aIt is a pleasure for us to introduce the proceedings of the second edition of theInternationalConferenceonHigh-PerformanceEmbeddedArchitecturesand Compilers (HiPEAC 2007). This conference ?lls a gap in that it focuses on how to meet the challenging performance requirements of future embedded systems through a concerted e?ort at both sides of the hardware/software interface. As a result, this year’s edition coveredtopic areasspanning from low-power,secure, and adaptive architectures via evaluation tools/methods to compiler optimi- tiontechniques.TheprogramalsofeaturedakeynotepresentationbyTomConte of North Carolina State University. This year we received 65 submissions of which 9 papers were committee - pers.Papersweresubmitted from15di?erent nations (about40 % fromEurope, 30% from Asia, and 30% from North America), which is a token of the global visibility of the conference. We had the luxury of having a strong Program Committee consisting of 34 experts in all areas within the scope of the conference and we kept all reviewing withintheProgramCommittee.Thus,eachpaperwastypicallyreviewedbyfour Program Committee members. We collected 258 reviews and we were happy to note that each paper was rigorously reviewed before any decisions were made, despite the fact that we shortened the review phase and that reviewing took place during most reviewers’ precious vacation time. | ||
| 650 | 0 | _aComputer science. | |
| 650 | 0 | _aData transmission systems. | |
| 650 | 0 | _aLogic design. | |
| 650 | 0 | _aComputer Communication Networks. | |
| 650 | 1 | 4 | _aComputer Science. |
| 650 | 2 | 4 | _aArithmetic and Logic Structures. |
| 650 | 2 | 4 | _aProcessor Architectures. |
| 650 | 2 | 4 | _aInput/Output and Data Communications. |
| 650 | 2 | 4 | _aLogic Design. |
| 650 | 2 | 4 | _aComputer Communication Networks. |
| 650 | 2 | 4 | _aProgramming Languages, Compilers, Interpreters. |
| 700 | 1 |
_aKaeli, David. _eeditor. |
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| 700 | 1 |
_aStenström, Per. _eeditor. |
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| 700 | 1 |
_aWhalley, David. _eeditor. |
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| 700 | 1 |
_aUngerer, Theo. _eeditor. |
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| 710 | 2 | _aSpringerLink (Online service) | |
| 773 | 0 | _tSpringer eBooks | |
| 776 | 0 | 8 |
_iPrinted edition: _z9783540693376 |
| 830 | 0 |
_aLecture Notes in Computer Science, _x0302-9743 ; _v4367 |
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| 856 | 4 | 0 | _uhttp://dx.doi.org/10.1007/978-3-540-69338-3 |
| 912 | _aZDB-2-SCS | ||
| 912 | _aZDB-2-LNC | ||
| 950 | _aComputer Science (Springer-11645) | ||
| 999 |
_c14749 _d14749 |
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