000 | 06005nam a22005895i 4500 | ||
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001 | 978-3-540-77560-7 | ||
003 | DE-He213 | ||
005 | 20201213201342.0 | ||
007 | cr nn 008mamaa | ||
008 | 100301s2008 gw | s |||| 0|eng d | ||
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_a9783540775607 _9978-3-540-77560-7 |
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024 | 7 |
_a10.1007/978-3-540-77560-7 _2doi |
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050 | 4 | _aQA76.9.C62 | |
072 | 7 |
_aUMB _2bicssc |
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072 | 7 |
_aUYF _2bicssc |
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072 | 7 |
_aCOM036000 _2bisacsh |
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082 | 0 | 4 |
_a004 _223 |
100 | 1 |
_aStenström, Per. _eeditor. |
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245 | 1 | 0 |
_aHigh Performance Embedded Architectures and Compilers _h[electronic resource] : _bThird International Conference, HiPEAC 2008, Göteborg, Sweden, January 27-29, 2008. Proceedings / _cedited by Per Stenström, Michel Dubois, Manolis Katevenis, Rajiv Gupta, Theo Ungerer. |
264 | 1 |
_aBerlin, Heidelberg : _bSpringer Berlin Heidelberg, _c2008. |
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300 | _bonline resource. | ||
336 |
_atext _btxt _2rdacontent |
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_acomputer _bc _2rdamedia |
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_aonline resource _bcr _2rdacarrier |
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_atext file _bPDF _2rda |
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490 | 1 |
_aLecture Notes in Computer Science, _x0302-9743 ; _v4917 |
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505 | 0 | _aInvited Program -- Supercomputing for the Future, Supercomputing from the Past (Keynote) -- I Multithreaded and Multicore Processors -- MIPS MT: A Multithreaded RISC Architecture for Embedded Real-Time Processing -- rMPI: Message Passing on Multicore Processors with On-Chip Interconnect -- Modeling Multigrain Parallelism on Heterogeneous Multi-core Processors: A Case Study of the Cell BE -- IIa Reconfigurable - ASIP -- BRAM-LUT Tradeoff on a Polymorphic DES Design -- Architecture Enhancements for the ADRES Coarse-Grained Reconfigurable Array -- Implementation of an UWB Impulse-Radio Acquisition and Despreading Algorithm on a Low Power ASIP -- IIb Compiler Optimizations -- Fast Bounds Checking Using Debug Register -- Studying Compiler Optimizations on Superscalar Processors Through Interval Analysis -- An Experimental Environment Validating the Suitability of CLI as an Effective Deployment Format for Embedded Systems -- III Industrial Processors and Application Parallelization -- Compilation Strategies for Reducing Code Size on a VLIW Processor with Variable Length Instructions -- Experiences with Parallelizing a Bio-informatics Program on the Cell BE -- Drug Design Issues on the Cell BE -- IV Power-Aware Techniques -- Coffee: COmpiler Framework for Energy-Aware Exploration -- Integrated CPU Cache Power Management in Multiple Clock Domain Processors -- Variation-Aware Software Techniques for Cache Leakage Reduction Using Value-Dependence of SRAM Leakage Due to Within-Die Process Variation -- V High-Performance Processors -- The Significance of Affectors and Affectees Correlations for Branch Prediction -- Turbo-ROB: A Low Cost Checkpoint/Restore Accelerator -- LPA: A First Approach to the Loop Processor Architecture -- VI Profiles: Collection and Analysis -- Complementing Missing and Inaccurate Profiling Using a Minimum Cost Circulation Algorithm -- Using Dynamic Binary Instrumentation to Generate Multi-platform SimPoints: Methodology and Accuracy -- Phase Complexity Surfaces: Characterizing Time-Varying Program Behavior -- VII Optimizing Memory Performance -- MLP-Aware Dynamic Cache Partitioning -- Compiler Techniques for Reducing Data Cache Miss Rate on a Multithreaded Architecture -- Code Arrangement of Embedded Java Virtual Machine for NAND Flash Memory -- Aggressive Function Inlining: Preventing Loop Blockings in the Instruction Cache. | |
520 | _aThe ?rst two editions of the HiPEAC conference series in Barcelona (2005) and Ghent (2007) have really demonstrated that the topics covered by HiPEAC attract a lot of interest. In the 2007 conference, about 200 people attended the conference and its satellite events. The third HiPEAC conference was held in G¨ oteborg, the second largest city in Sweden. The o?erings of this conference were rich and diverse. We o?ered attendees a set of four workshops on topics that are all central to the HiPEAC roadmap: multi-cores, compiler optimizations, recon?gurable computing, and interconn- tion networks. Additionally, a tutorial on the Sun?ower Toolsuite was o?ered. The conference program was as rich as in the last years. It featured many important and timely topics such as multi-core processors, recon?gurable s- tems, compiler optimization, power-aware techniques and more. The conference also o?ered a keynote speech by Mateo Valero – the Eckert-Mauchly Award winner in 2007. Several social events provided opportunities for interaction and exchange of ideas in informal settings such as a tour at the Universeum – a science exhibition center and aquarium – where the banquet took place as well. This yearwe received77 submissions of which 14 paperswereCommittee - pers. Papers were submitted from 22 di?erent nations (about 40% from Europe, 25% from Asia, 30% from North America and 5% from South America), which is a token of the global visibility of the conference. | ||
650 | 0 | _aComputer science. | |
650 | 0 | _aData transmission systems. | |
650 | 0 | _aLogic design. | |
650 | 0 | _aComputer Communication Networks. | |
650 | 1 | 4 | _aComputer Science. |
650 | 2 | 4 | _aArithmetic and Logic Structures. |
650 | 2 | 4 | _aProcessor Architectures. |
650 | 2 | 4 | _aInput/Output and Data Communications. |
650 | 2 | 4 | _aLogic Design. |
650 | 2 | 4 | _aComputer Communication Networks. |
650 | 2 | 4 | _aProgramming Languages, Compilers, Interpreters. |
700 | 1 |
_aDubois, Michel. _eeditor. |
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700 | 1 |
_aKatevenis, Manolis. _eeditor. |
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700 | 1 |
_aGupta, Rajiv. _eeditor. |
|
700 | 1 |
_aUngerer, Theo. _eeditor. |
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710 | 2 | _aSpringerLink (Online service) | |
773 | 0 | _tSpringer eBooks | |
776 | 0 | 8 |
_iPrinted edition: _z9783540775591 |
830 | 0 |
_aLecture Notes in Computer Science, _x0302-9743 ; _v4917 |
|
856 | 4 | 0 | _uhttp://dx.doi.org/10.1007/978-3-540-77560-7 |
912 | _aZDB-2-SCS | ||
912 | _aZDB-2-LNC | ||
950 | _aComputer Science (Springer-11645) | ||
999 |
_c15417 _d15417 |