000 04189nam a22005415i 4500
001 978-3-642-00904-4
003 DE-He213
005 20201213201517.0
007 cr nn 008mamaa
008 100301s2009 gw | s |||| 0|eng d
020 _a9783642009044
_9978-3-642-00904-4
024 7 _a10.1007/978-3-642-00904-4
_2doi
050 4 _aQA76.9.C62
072 7 _aUMB
_2bicssc
072 7 _aUYF
_2bicssc
072 7 _aCOM036000
_2bisacsh
082 0 4 _a004
_223
100 1 _aStenström, Per.
_eeditor.
245 1 0 _aTransactions on High-Performance Embedded Architectures and Compilers II
_h[electronic resource] /
_cedited by Per Stenström.
264 1 _aBerlin, Heidelberg :
_bSpringer Berlin Heidelberg,
_c2009.
300 _aXIV, 327 p.
_bonline resource.
336 _atext
_btxt
_2rdacontent
337 _acomputer
_bc
_2rdamedia
338 _aonline resource
_bcr
_2rdacarrier
347 _atext file
_bPDF
_2rda
490 1 _aLecture Notes in Computer Science,
_x0302-9743 ;
_v5470
505 0 _aSpecial Section on High-Performance Embedded Architectures and Compilers -- Recruiting Decay for Dynamic Power Reduction in Set-Associative Caches -- Compiler-Assisted Memory Encryption for Embedded Processors -- Branch Predictor Warmup for Sampled Simulation through Branch History Matching -- Data Cache Techniques to Save Power and Deliver High Performance in Embedded Systems -- Combining Edge Vector and Event Counter for Time-Dependent Power Behavior Characterization -- Regular Papers -- Accurate Instruction Pre-scheduling in Dynamically Scheduled Processors -- Fetch Gating Control through Speculative Instruction Window Weighting -- Fast Code Generation for Embedded Processors with Aliased Heterogeneous Registers -- Linux Kernel Compaction through Cold Code Swapping -- Complexity Effective Bypass Networks -- A Context-Parameterized Model for Static Analysis of Execution Times -- Reexecution and Selective Reuse in Checkpoint Processors -- Compiler Support for Code Size Reduction Using a Queue-Based Processor -- Power-Aware Bus Coscheduling for Periodic Realtime Applications Running on Multiprocessor SoC -- Performance Characterization for the Implementation of Content Addressable Memories Based on Parallel Hashing Memories.
520 _aTransactions on HiPEAC aims at the timely dissemination of research contributions in computer architecture and compilation methods for high-performance embedded computer systems. Recognizing the convergence of embedded and general-purpose computer systems, this journal publishes original research on systems targeted at specific computing tasks as well as systems with broad application bases. The scope of the journal therefore covers all aspects of computer architecture, code generation and compiler optimization methods of interest to researchers and practitioners designing future embedded systems. This second issue contains 15 papers carefully reviewed and selected out of 31 submissions and is divided into two sections. The first section contains extended versions of the top five papers from the 2nd International Conference on High-Performance Embedded Architectures and Compilers (HiPEAC 2007) held in Ghent, Belgium, in January 2007. The second section consists of ten papers covering topics such as microarchitecture, memory systems, code generation, and performance modeling.
650 0 _aComputer science.
650 0 _aData transmission systems.
650 0 _aLogic design.
650 0 _aComputer Communication Networks.
650 1 4 _aComputer Science.
650 2 4 _aArithmetic and Logic Structures.
650 2 4 _aProcessor Architectures.
650 2 4 _aInput/Output and Data Communications.
650 2 4 _aLogic Design.
650 2 4 _aComputer Communication Networks.
650 2 4 _aProgramming Languages, Compilers, Interpreters.
710 2 _aSpringerLink (Online service)
773 0 _tSpringer eBooks
776 0 8 _iPrinted edition:
_z9783642009037
830 0 _aLecture Notes in Computer Science,
_x0302-9743 ;
_v5470
856 4 0 _uhttp://dx.doi.org/10.1007/978-3-642-00904-4
912 _aZDB-2-SCS
912 _aZDB-2-LNC
950 _aComputer Science (Springer-11645)
999 _c15945
_d15945