000			05135nam a22005895i 4500
001			978-3-642-11515-8
003			DE-He213
005			20201213201722.0
007			cr nn 008mamaa
008			100301s2010 gw | s |||| 0|eng d
020			_a9783642115158 _9978-3-642-11515-8
024	7		_a10.1007/978-3-642-11515-8 _2doi
050		4	_aQA76.9.C62
072		7	_aUMB _2bicssc
072		7	_aUYF _2bicssc
072		7	_aCOM036000 _2bisacsh
082	0	4	_a004 _223
100	1		_aPatt, Yale N. _eeditor.
245	1	0	_aHigh Performance Embedded Architectures and Compilers _h[electronic resource] : _b5th International Conference, HiPEAC 2010, Pisa, Italy, January 25-27, 2010. Proceedings / _cedited by Yale N. Patt, Pierfrancesco Foglia, Evelyn Duesterwald, Paolo Faraboschi, Xavier Martorell.
264		1	_aBerlin, Heidelberg : _bSpringer Berlin Heidelberg, _c2010.
300			_aXIII, 364p. 76 illus. _bonline resource.
336			_atext _btxt _2rdacontent
337			_acomputer _bc _2rdamedia
338			_aonline resource _bcr _2rdacarrier
347			_atext file _bPDF _2rda
490	1		_aLecture Notes in Computer Science, _x0302-9743 ; _v5952
505	0		_aInvited Program -- Embedded Systems as Datacenters -- Larrabee: A Many-Core Intel Architecture for Visual Computing -- Architectural Support for Concurrency -- Remote Store Programming -- Low-Overhead, High-Speed Multi-core Barrier Synchronization -- Improving Performance by Reducing Aborts in Hardware Transactional Memory -- Energy and Throughput Efficient Transactional Memory for Embedded Multicore Systems -- Compilation and Runtime Systems -- Split Register Allocation: Linear Complexity Without the Performance Penalty -- Trace-Based Data Layout Optimizations for Multi-core Processors -- Buffer Sizing for Self-timed Stream Programs on Heterogeneous Distributed Memory Multiprocessors -- Automatically Tuning Sparse Matrix-Vector Multiplication for GPU Architectures -- Reconfigurable and Customized Architectures -- Virtual Ways: Efficient Coherence for Architecturally Visible Storage in Automatic Instruction Set Extensions -- Accelerating XML Query Matching through Custom Stack Generation on FPGAs -- An Application-Aware Load Balancing Strategy for Network Processors -- Memory-Aware Application Mapping on Coarse-Grained Reconfigurable Arrays -- Multicore Efficiency, Reliability, and Power -- Maestro: Orchestrating Lifetime Reliability in Chip Multiprocessors -- Combining Locality Analysis with Online Proactive Job Co-scheduling in Chip Multiprocessors -- RELOCATE: Register File Local Access Pattern Redistribution Mechanism for Power and Thermal Management in Out-of-Order Embedded Processor -- Performance and Power Aware CMP Thread Allocation Modeling -- Memory Organization and Optimization -- Multi-level Hardware Prefetching Using Low Complexity Delta Correlating Prediction Tables with Partial Matching -- Scalable Shared-Cache Management by Containing Thrashing Workloads -- SRP: Symbiotic Resource Partitioning of the Memory Hierarchy in CMPs -- DIEF: An Accurate Interference Feedback Mechanism for Chip Multiprocessor Memory Systems -- Programming and Analysis of Accelerators -- Tagged Procedure Calls (TPC): Efficient Runtime Support for Task-Based Parallelism on the Cell Processor -- Analysis of Task Offloading for Accelerators -- Offload – Automating Code Migration to Heterogeneous Multicore Systems -- Computer Generation of Efficient Software Viterbi Decoders.
520			_aThis book constitutes the refereed proceedings of the 5th International Conference on High Performance Embedded Architectures and Compilers, HiPEAC 2010, held in Pisa, Italy, in January 2010. The 23 revised full papers presented together with the abstracts of 2 invited keynote addresses were carefully reviewed and selected from 94 submissions. The papers are organized in topical sections on architectural support for concurrency; compilation and runtime systems; reconfigurable and customized architectures; multicore efficiency, reliability, and power; memory organization and optimization; and programming and analysis of accelerators.
650		0	_aComputer science.
650		0	_aData transmission systems.
650		0	_aLogic design.
650		0	_aComputer Communication Networks.
650	1	4	_aComputer Science.
650	2	4	_aArithmetic and Logic Structures.
650	2	4	_aProcessor Architectures.
650	2	4	_aInput/Output and Data Communications.
650	2	4	_aLogic Design.
650	2	4	_aComputer Communication Networks.
650	2	4	_aProgramming Languages, Compilers, Interpreters.
700	1		_aFoglia, Pierfrancesco. _eeditor.
700	1		_aDuesterwald, Evelyn. _eeditor.
700	1		_aFaraboschi, Paolo. _eeditor.
700	1		_aMartorell, Xavier. _eeditor.
710	2		_aSpringerLink (Online service)
773	0		_tSpringer eBooks
776	0	8	_iPrinted edition: _z9783642115141
830		0	_aLecture Notes in Computer Science, _x0302-9743 ; _v5952
856	4	0	_uhttp://dx.doi.org/10.1007/978-3-642-11515-8
912			_aZDB-2-SCS
912			_aZDB-2-LNC
950			_aComputer Science (Springer-11645)
999			_c16568 _d16568