000 04213nam a22004455i 4500
001 978-94-91216-33-6
003 DE-He213
005 20201213202816.0
007 cr nn 008mamaa
008 120301s2010 fr | s |||| 0|eng d
020 _a9789491216336
_9978-94-91216-33-6
024 7 _a10.2991/978-94-91216-33-6
_2doi
050 4 _aTK7895.M4
050 4 _aTK7895.M4
072 7 _aUKS
_2bicssc
072 7 _aUYF
_2bicssc
072 7 _aCOM067000
_2bisacsh
082 0 4 _a004.53
_223
100 1 _aAbdallah, Abderazek Ben.
_eauthor.
245 1 0 _aMulticore Systems On-Chip: Practical Software/Hardware Design
_h[electronic resource] /
_cby Abderazek Ben Abdallah.
264 1 _aParis :
_bAtlantis Press,
_c2010.
300 _aXVIII, 180p.
_bonline resource.
336 _atext
_btxt
_2rdacontent
337 _acomputer
_bc
_2rdamedia
338 _aonline resource
_bcr
_2rdacarrier
347 _atext file
_bPDF
_2rda
490 1 _aAtlantis Ambient and Pervasive Intelligence,
_x1875-7669 ;
_v3
505 0 _aMulticore Systems Design Methodology -- Design for Low Power Systems -- Network-on-Chip for Multi- and Many-Core Systems -- Parallelizing Compiler for High Performance Computing -- Dual-Execution Processor Architecture for Embedded Computing -- Low Power Embedded Core Architecture -- ReconfigurableMulticore Architectures.
520 _aConventional on-chip communication design mostly use ad-hoc approaches that fail to meet the challenges posed by the next-generation MultiCore Systems on-chip (MCSoC) designs. These major challenges include wiring delay, predictability, diverse interconnection architectures, and power dissipation. A Network-on-Chip (NoC) paradigm is emerging as the solution for the problems of interconnecting dozens of cores into a single system on-chip. However, there are many problems associated with the design of such systems. These problems arise from non-scalable global wire delays, failure to achieve global synchronization, and difficulties associated with non-scalable bus-based functional interconnects. The book consists of three parts, with each part being subdivided into four chapters. The first part deals with design and methodology issues. The architectures used in conventional methods of MCSoCs design and custom multiprocessor architectures are not flexible enough to meet the requirements of different application domains and not scalable enough to meet different computation needs and different complexities of various applications. Several chapters of the first part will emphasize on the design techniques and methodologies. The second part covers the most critical part of MCSoCs design — the interconnections. One approach to addressing the design methodologies is to adopt the so-called reusability feature to boost design productivity. In the past years, the primitive design units evolved from transistors to gates, finite state machines, and processor cores. The network-on-chip paradigm offers this attractive property for the future and will be able to close the productivity gap. The last part of this book delves into MCSoCs validations and optimizations. A more qualitative approach of system validation is based on the use of formal techniques for hardware design. The main advantage of formal methods is the possibility to prove the validity of essential design requirements. As formal languages have a mathematical foundation, it is possible to formally extract and verify these desired properties of the complete abstract state space. Online testing techniques for identifying faults that can lead to system failure are also surveyed. Emphasis is given to analytical redundancy-based techniques that have been developed for fault detection and isolation in the automatic control area.
650 0 _aComputer science.
650 0 _aMemory management (Computer science).
650 1 4 _aComputer Science.
650 2 4 _aMemory Structures.
710 2 _aSpringerLink (Online service)
773 0 _tSpringer eBooks
830 0 _aAtlantis Ambient and Pervasive Intelligence,
_x1875-7669 ;
_v3
856 4 0 _uhttp://dx.doi.org/10.2991/978-94-91216-33-6
912 _aZDB-2-SCS
950 _aComputer Science (Springer-11645)
999 _c19903
_d19903