000 | 03804nam a22005175i 4500 | ||
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001 | 978-1-4020-5897-4 | ||
003 | DE-He213 | ||
005 | 20201213203208.0 | ||
007 | cr nn 008mamaa | ||
008 | 100301s2007 ne | s |||| 0|eng d | ||
020 |
_a9781402058974 _9978-1-4020-5897-4 |
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024 | 7 |
_a10.1007/978-1-4020-5897-4 _2doi |
|
050 | 4 | _aTK7888.4 | |
072 | 7 |
_aTJFC _2bicssc |
|
072 | 7 |
_aTEC008010 _2bisacsh |
|
082 | 0 | 4 |
_a621.3815 _223 |
100 | 1 |
_aVerma, Manish. _eauthor. |
|
245 | 1 | 0 |
_aAdvanced Memory Optimization Techniques for Low-Power Embedded Processors _h[electronic resource] / _cby Manish Verma, Peter Marwedel. |
264 | 1 |
_aDordrecht : _bSpringer Netherlands, _c2007. |
|
300 |
_a161 p. _bonline resource. |
||
336 |
_atext _btxt _2rdacontent |
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337 |
_acomputer _bc _2rdamedia |
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338 |
_aonline resource _bcr _2rdacarrier |
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347 |
_atext file _bPDF _2rda |
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505 | 0 | _aRelated Work -- Memory Aware Compilation and Simulation Framework -- Non-Overlayed Scratchpad Allocation Approaches for Main/Scratchpad Memory Hierarchy -- Non-Overlayed Scratchpad Allocation Approaches for Main/Scratchpad + Cache Memory Hierarchy -- Scratchpad Overlay Approaches for Main/Scratchpad Memory Hierarchy -- Data Partitioning and Loop Nest Splitting -- Scratchpad Sharing Strategies for Multiprocess Applications -- Conclusions and Future Directions. | |
520 | _aThe design of embedded systems warrants a new perspective because of the following two reasons: Firstly, slow and energy inefficient memory hierarchies have already become the bottleneck of the embedded systems. It is documented in the literature as the memory wall problem. Secondly, the software running on the contemporary embedded devices is becoming increasingly complex. It is also well understood that no silver bullet exists to solve the memory wall problem. Therefore, this book explores a collaborative approach by proposing novel memory hierarchies and software optimization techniques for the optimal utilization of these memory hierarchies. Linking memory architecture design with memory-architecture aware compilation results in fast, energy-efficient and timing predictable memory accesses. The evaluation of the optimization techniques using real-life benchmarks for a single processor system, a multiprocessor system-on-chip (SoC) and for a digital signal processor system, reports significant reductions in the energy consumption and performance improvement of these systems. The book presents a wide range of optimizations, progressively increasing in the complexity of analysis and of memory hierarchies. The final chapter covers optimization techniques for applications consisting of multiple processes found in most modern embedded devices. Advanced Memory Optimization Techniques for Low Power Embedded Processors is designed for researchers, complier writers and embedded system designers / architects who wish to optimize the energy and performance characteristics of the memory subsystem. | ||
650 | 0 | _aEngineering. | |
650 | 0 | _aMemory management (Computer science). | |
650 | 0 | _aSoftware engineering. | |
650 | 0 | _aComputer system performance. | |
650 | 0 | _aComputer science. | |
650 | 0 | _aSystems engineering. | |
650 | 1 | 4 | _aEngineering. |
650 | 2 | 4 | _aCircuits and Systems. |
650 | 2 | 4 | _aProgramming Languages, Compilers, Interpreters. |
650 | 2 | 4 | _aMemory Structures. |
650 | 2 | 4 | _aSpecial Purpose and Application-Based Systems. |
650 | 2 | 4 | _aSystem Performance and Evaluation. |
700 | 1 |
_aMarwedel, Peter. _eauthor. |
|
710 | 2 | _aSpringerLink (Online service) | |
773 | 0 | _tSpringer eBooks | |
776 | 0 | 8 |
_iPrinted edition: _z9781402058967 |
856 | 4 | 0 | _uhttp://dx.doi.org/10.1007/978-1-4020-5897-4 |
912 | _aZDB-2-ENG | ||
950 | _aEngineering (Springer-11647) | ||
999 |
_c20641 _d20641 |